The present invention relates to a multi-component system including a plurality of components connected via a common bus such as a Local Area Network (LAN) to each other, each of the component including at least a Central Processing Unit (CPU), and in particular to, a scheme of resetting a CPU which is in an abnormal condition in any one of the components.
In the prior art, there is known a multi-CPU system in which a plurality of CPUs are connected via a common bus including a reset line to each other and the overall processing is divided among the CPUs. For example, JP-A-5-290008 describes a technique for such multi-CPU system in which a CPU is reset according to designation from an application in execution.
The technique is used in a system including a plurality of sub-racks (components) each of which including at least a CPU module. During the operation of the system, when an application program being executed by a CPU module of either one of the subracks indicates a system reset, a system reset request is issued. The CPU module acquires the right to reset and then resets a CPU module in an associated sub-rack via the reset line.